Assessment of 3D mesh watermarking techniques

With the increasing usage of three-dimensional meshes in Computer-Aided Design (CAD), medical imaging, and entertainment fields like virtual reality, etc., the authentication problems and awareness of intellectual property protection have risen since the last decade. Numerous watermarking schemes have been suggested to protect ownership and prevent the threat of data piracy. This paper begins with the potential difficulties that arose when dealing with three-dimension entities in comparison to two-dimensional entities and also lists possible algorithms suggested hitherto and their comprehensive analysis. Attacks, also play a crucial role in deciding a watermarking algorithm so an attack based analysis is also presented to analyze resilience of watermarking algorithms under several attacks. In the end, some evaluation measures and potential solutions are brooded over to design robust and oblivious watermarking schemes in the future

On Improving the Performance of Dynamic DCVSL Circuits

This contribution aims at improving the performance of Dynamic Differential Cascode Voltage Switch Logic (Dy-DCVSL) and Enhanced Dynamic Differential Cascode Voltage Switch Logic (EDCVSL) and suggests three architectures for the same. The first architecture uses transmission gates (TG) to reduce the logic tree depth and width, which results in speed improvement. As leakage is a dominant issue in lower technology nodes, the second architecture is proposed by adapting the leakage control technique (LECTOR) in Dy-DCVSL and EDCVSL. The third proposed architecture combines features of both the first and the second architectures. The operation of the proposed architectures has been verified through extensive simulations with different CMOS submicron technology nodes (90 nm, 65 nm, and 45 nm). The delay of the gates based on the first architecture remains almost the same for different functionalities. It is also observed that Dy-DCVSL gates are 1.6 to 1.4 times faster than their conventional counterpart. The gates based on the second architecture show a maximum of 74.3% leakage power reduction. Also, it is observed that the percentage of reduction in leakage power increases with technology scaling. Lastly, the gates based on the third architecture achieve similar leakage power reduction values to the second one but are not able to exhibit the same speed advantage as achieved with the first architecture